I. Field
The present disclosure relates generally to electronics, and more specifically to techniques for generating relative addresses.
II. Background
Processors are widely used for various applications such as communication, computing, data networking, etc. A processor may perform various operations on data stored in a storage unit, which may be a register file, a random access memory (RAM), etc. The data for an operation may be specified by either an absolute address or a relative address. An absolute address points to a specific location in the storage unit where the data is stored. A relative address is given by a base address and an offset. The base address points to a reference location in the storage unit. The offset indicates the distance between the reference location and the actual location where the data is stored. A relative address is typically converted to an absolute address, which is then used to fetch the desired data from the storage unit.
As an example, an instruction to add two operands may be given as:add r0, x0[r1+15], r2.The first operand is stored in register/location r2. The second operand is stored at a location determined by a base value stored in register r1 and an offset of 15. The result of the sum of the two operands is stored in register/location r0.
The above instruction is typically converted to two instructions, as follows:add a0, r1, 15add r0, x0[a0], r2.The first instruction computes an absolute address for the second operand by summing the base value in register r1 with the offset of 15 and then storing the absolute address in register a0. The second instruction computes the sum of the two operands, with the second operand being determined by the absolute address computed by the first instruction. An arithmetic logic unit (ALU) may perform the computation for both the first and second instructions.
Converting a single instruction with relative addressing to two instructions may be undesirable for several reasons. First, the computation of the absolute address by the first instruction consumes ALU resources. Second, longer delay may be experienced to complete the two instructions in a sequential order, since the second instruction is dependent on the result of the first instruction. This delay penalty is more severe when the ALU have multiple stages. The longer delay due to the multiple ALU stages may adversely impact performance.
There is therefore a need in the art for techniques to efficiently handle relative addressing.